// Generated for: spectre
// Generated on: Mar 30 12:08:51 2010
// Design library name: ece3663
// Design cell name: 2inputXOR
// Design view name: schematic
simulator lang=spectre
global 0

// Library name: ece3663
// Cell name: 2inputNAND
// View name: schematic
subckt TeamXOR2inNAND VDD VSS Vin1 Vin2 Vout
parameters wp0=wp1 wn0=wn1 ln0=600n lp0=600n mult0=1
    P1 (Vout Vin1 VDD VDD) ami06P w=wp0 l=lp0 as=wn1*wp0 ad=wn1*wn0 ps=wp1+wp0 pd=wp1+wp0 m=mult0
    P0 (Vout Vin2 VDD VDD) ami06P w=wp0 l=lp0 as=wn1*wp0 ad=wn1*wn0 ps=wp1+wp0 pd=wp1+wp0 m=mult0
    N1 (net50 Vin2 VSS VSS) ami06N w=wn0 l=ln0 as=wn1*2*wn0 ad=wn1*2*wn0 ps=wp1+2*wn0 pd=wp1+2*wn0 m=mult0
    N0 (Vout Vin1 net50 VSS) ami06N w=wn0 l=ln0 as=wn1*2*wn0 ad=wn1*2*wn0 ps=wp1+2*wn0 pd=wp1+2*wn0 m=mult0
ends TeamXOR2inNAND
// End of subcircuit definition.

// Library name: ece3663
// Cell name: 2inputXOR
// View name: schematic
subckt TeamXOR2inXOR VDD VSS inA inB out
parameters wp1=3u wn1=1.5u ln1=600n lp0=600n mult0=1
I3 (VDD VSS inA inB net10) TeamXOR2inNAND wp0=wp1 wn0=wn1 ln0=ln1 lp0=lp1 mult0=1
I2 (VDD VSS net10 inB net15) TeamXOR2inNAND wp0=wp1 wn0=wn1 ln0=ln1 lp0=lp1 mult0=1
I1 (VDD VSS net25 net15 Vout) TeamXOR2inNAND wp0=wp1 wn0=wn1 ln0=ln1 lp0=lp1 mult0=1
I0 (VDD VSS inA net10 net25) TeamXOR2inNAND wp0=wp1 wn0=wn1 ln0=ln1 lp0=lp1 mult0=1

// 2 input AND Gate
subckt TeamXOR2inAND Vdd Vss InA InB Out 
parameters wp=3u wn=1.5u ln=600n lp=600n mult=1 
	P2 (Out net049 Vdd Vdd) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp pd=3u+wp m=mult
	P1 (net049 InB Vdd Vdd) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp pd=3u+wp m=mult
	P0 (net049 InA Vdd Vdd) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp pd=3u+wp m=mult 
	N2 (Out net049 Vss Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn pd=3u+wn m=mult
	N1 (net22 InB Vss Vss) ami06N w=2*wn l=ln as=1.5u*2*wn ad=1.5u*2*wn ps=3u+2*wn pd=3u+2*wn m=mult
	N0 (net049 InA net22 Vss) ami06N w=2*wn l=ln as=1.5u*2*wn ad=1.5u*2*wn ps=3u+2*wn pd=3u+2*wn m=mult
ends TeamXOR2inAND
// end of subcircuit definition.

// Subcircuit Definition of Half Adder
subckt TeamXORHalfAdder VDD VSS inA inB S Cout
parameters wp1=3u wn1=1.5u ln1=600n lp1=600n mult=1
	I1 (VDD VSS inA inB S) TeamXOR2inXOR wp1=3u wn1=1.5u ln1=600n lp0=600n mult0=1
	I0 (VDD VSS inA inB Cout) TeamXOR2inAND wp=3u wn=1.5u ln=600n lp=600n mult=1 
ends TeamXORHalfAdder
// end of subcircuit definition.
